Is there support for Xtensa LX7 cores?

I can't express how excited I am for the recent progress in embedded Swift.

Is there support for the Xtensa LX7 core yet? It's used in the ESP32-S3, which is used in a very popular line of boards that I’d love to be able to target.


Unfortunately support for the Xtensa ISA is maintained in an Espressif fork of LLVM. If this is something you're interested in, the best step would be helping figure out how to upstream their diff to LLVM so Swift can use them.

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At least the description says “To be upstreamed.” I opened this issue with them to hopefully bring attention to it.

I know @kubamracek was poking at that - from what I understand as soon as they are able to get that merged upstream the Swift side of it is VERY trivial.


I'm also very interested on supporting swift on xtensa chips. Also, I'm intrigued because i've seen the esp-rs efforts to bring rust to esp socs, and they have good support for the xtensa chips, and they seem to use llvm too: GitHub - esp-rs/rust: Rust for the xtensa architecture. Built in targets for the ESP32 and ESP8266

I don't know much about compilers and these kinda stuff so I'm very likely wrong, but also just curious about the details of this implementation

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Just adding my +1 — can’t contribute very much to compilers and such but ESP32-S3 is my microcontroller of choice as of late and it would be fantastic to use Embedded Swift in those projects.

There’s already a progress tracking issue on their repo and it’s only lacking on checkmark. I don’t know if this means they’re close to done?

According to that comment, they've sent patches upstream, as of a couple of days ago. I don't know if that's everything, or how long it will take LLVM to accept them.

Also interested in Xtensa support.

In Embedded Swift Example Projects for ARM and RISC-V Microcontrollers - #13 by kubamracek @kubamracek mentioned that llvm backend support isn't enough, that we need clang support as well. Does anyone know if anybody is working on this?

I'm also adding my +1 for the support of those chips and I'd be glad to help for potential tasks that don't require too much compiler-related skills if you have some!

Seems that PR is moving forward fast :rocket:

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Doesn’t seem that fast to me. They’re estimating next year, mostly due to the long turnaround getting PRs reviewed.

Probably we need to merge about 30-40 patches to implement most of functionality to be able generate Rust code and compile ESP-IDF examples:

  1. Currently we have 10 prepared patches with base functionality not upstreamed (Tracking Issue for merging to upstream (LLVM-57) #4 (comment)). This patches are not very large, so I think optimistic estimation is to spend 1-1,5 week on each patch to upstream.
    So process in optimal way will be finished in September.
  2. Implement other Xtensa features like Window, Boolean, Float, etc. It is about 8-12 patches. Also in optimistic case will take another 3 month and wiil be finished in November.
  3. Implement Xtensa targets in Clang esp32,esp8266, etc" and add support for multilib and linker. It is about 8-12 patches. Some of these patches will be complex, so in optimistic case will take another 2-3 month and will be finished in January/Febraury.
    In a pessimistic case, this process may take another 2-4 months.

+1 from my side, too. I'm very interested in support for xtensa chips. :+1:t3: